1. Field of the Invention
The present invention relates in general to a process for fabricating flash electrically erasable and programmable read-only memory (flash EEPROM) devices. In particular, the present invention relates to a process for fabricating flash EEPROM devices having improved programing and accessing speed characteristics.
2. Technical Background
The flash EEPROM is one of the semiconductor memory devices that are enjoying the progress in device miniaturization brought about by the sustained advancements in the semiconductor fabrication technology. However, as component dimensions continue to shrink, the surface area of the floating gate in the memory cell transistor is also being reduced, which results in the degradation of the coupling ratio for the applied voltage at the control gate of the memory cell transistor. The direct effect is the limitation, even degradation, of the speed characteristics of memory cell programming and accessing operations.
A brief description of a conventional flash EEPROM device is included below to assist in the understanding of the present invention. FIG. 1 schematically shows the top view of the memory cells of a conventional flash EEPROM device. FIG. 2 schematically shows a cross-sectional view of the memory cells of the conventional flash EEPROM device of FIG. 1 as taken along the II--II line. A simultaneous reference to the two drawings will help explain the flash EEPROM device of the prior art.
As is seen in FIGS. 1 and 2, P-type silicon substrate 10 is utilized as the basis for the construction of the flash EEPROM device. N.sup.+ type buried bit lines 100 are formed within P-type silicon substrate 10, those of which surrounded by N.sup.- doped region 102 that serves as the source region for a memory cell transistor of the flash EEPROM device. Tunnel oxide layers 110 are formed over the surface of P-type substrate 10, and are covered by floating gates 120. Inter-gate dielectric layers 130 are further formed over floating gates 120, with control gates 140 formed further on top that serve as the word lines for the flash EEPROM device.
However, as flash EEPROM devices are fabricated in ever finer resolutions, the surface area of floating gates 120 also shrinks. This leads directly to a decrease in capacitance of the effective capacitor formed between the layer of floating gate 120 and the layer of control gate 140. This decrease in effective capacitance results in a reduction of the coupling ratio, which is a parameter that describes the coupling to floating gate 120 of the voltage applied to control gate 140. The poorly-coupled voltage to floating gate 120 limits the programming and accessing speed characteristics of the flash EEPROM device.